Shiwei Liu is an Assistant Professor in the Department of Electronic and Information Engineering at Tongji University. He received the Ph.D. degree in 2024 from the Institute of Microelectronics, Fudan University, under the supervision of Prof. Qi Liu and Prof. Chixiao Chen, selected for the CCF Incentive Program for Doctoral Dissertations in Integrated Circuit Design (CCF集成电路设计专业委员会博士学位论文激励计划). Dr.Liu’s research interests include AI chip, in-memory computing and 2.5D/3D chip. He has published over 20 papers in top-tier conferences and journals in the field of integrated circuits and computer architecture, including ISSCC, CICC, DAC, ICCAD, TCAS-I, etc.

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Research Interests

• Architecture–algorithm co-design for efficient AI with model compression.
• Compute-in-memory circuit and architecture design for AI acceleration.
• Scalable 2.5D/3D chiplet architecture and chip design.

News

• 07/10/2026 A 3D DRAM thermal-aware scheduler “AMBER: Thermal-Aware Spatio-Temporal Scheduling for Edge LLM Inference on 3D DRAM-on-NPU Systems” was accepted by AICAS 2026.
• 06/05/2026 A DiT video generation accelerator “DiFlash: a 13.70TOPS/W 156.05Pixels/mJ Video Generation Accelerator with Bubble-Free Online-Quantized FlashAttention and Query-Reuse Sliding-Tile Attention” was accepted by ESSCIRC 2026.
• 05/13/2026 I was selected as a Session Co-Chair for “Quantization, Approximation, and Compression for ML Hardware I” at the ISCAS 2026 in Shanghai.
• 05/01/2026 I have joined Tongji University as an Assistant Professor. A new journey begins!
• 04/22/2026 A multi-core TPU processor “An 11.16 μJ/token Edge SLM Decoder Accelerator with Scalable Ring-based Configuration for Token-level Pipelining in 16nm FinFET” was accepted and presented at IEEE CICC 2026.
• 04/03/2026 An spike sorting processor “A 1024-Ch 583-nW/Ch Spike-Sorting SoC With Sparsity-Aware Spike Detection Scratchpad and Ultra-Low-Leakage Dual-Voltage 5T-SRAM for 16K-Template Clustering” get accepted by TCAS-I.
• 02/03/2026 An LLM computing-in-memory accelerator “Scalable Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper and Local Attention Reusable Engine for Semi-Structured-Pruned NN” get accepted by JETCAS.

Professional Experience

May 2026 - Present: Tongji University

• Assistant Professor (Since May. 2026)
• Department of Electronic and Information Engineering at Tongji University.

May. 2025 - Apr. 2026: Fudan Shaoxin Laboratory

• Research Fellow, working with Prof. Prof. Chixiao Chen.
• Custom Intelligent Hardware (CIH) Lab.

Nov. 2023 - Dec. 2024: University of Michigan

• Research Fellow, working with Prof. Mehdi Saligane. (Jun. 2024 - Dec. 2024)
• Visiting Researcher, working with Prof. Mehdi Saligane. (Nov. 2023 - Jun. 2024)
• Department of Electronic and Computer Engineering.

Sept. 2023 - Jan. 2024: Google Research

• Ph.D. Research, working with Gregory Kielian and Bangfei Pan.

Education Experience

Sep. 2021 - Jun. 2024: Fudan University

• Ph.D. in ‌Electronic Engineering‌, under the supervision of Prof. Qi Liu and Prof. Chixiao Chen.
• Dissertation: Enhancing Large Language Model Acceleration through Computing-in-Memory Technology (CCF Incentive Program for Doctoral Dissertations in Integrated Circuit Design).
• Shanghai Outstanding Graduate.
• National Scholarship for Ph.D. Students (1%, 2023).

Sep. 2018 - Jun. 2021: Fudan University

• M.S. in Microelectronics and Solid-State Electronics, under the supervision of Prof. Richard Shi.
• Shanghai Outstanding Graduate.

Sep. 2014 - Jun. 2018: Fudan University

• B.S. in Microelectronics Science and Engineering.

Course Teaching

• Digital Integrated Circuit Design

Contact

We are looking for undergrad/master/Ph.D students with background of EE/CS, especially IC design, computer archiecture and alorightms.

• Address 1: 4800 Cao’an Road, Zhixin Building, Jiading District, Shanghai, China, 201804.
• Address 2: 2005 Songhu Road, Cross Building 1, Yangpu District, Shanghai, China, 200438.