Selected Publications

Conference Papers

[AICAS’26] X. Lin, S. Jia, H. Zhu, X. Jia, S. Liu*, Chixiao Chen, “AMBER: Thermal-Aware Spatio-Temporal Scheduling for Edge LLM Inference on 3D DRAM-on-NPU Systems,” IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2026. (Corresponding Author)

[ESSCIRC’26] J. Liu, S. Liu*, L. Ding, S. Li, T. Zhao, Y. Zhang, X. Li, S. Huang, J. Li, Q. Luo, Y. Dai, J. Li, S Zeng, C. Chen, G. Dai, “DiFlash: A 13.70TOPS/W 156.05Pixels/mJ Video Generation Accelerator with Bubble-Free Online-Quantized FlashAttention and Query-Reuse Sliding-Tile Attention,” IIEEE European Solid-State Electronics Research Conference (ESSCIRC), 2026. (Co-First Author)

[CICC’26] G. Tao, J. Luo, S. Liu*, A. Li, G. Kielian, K. Lei, Q. Zhang, D. Sylvester, M. Saligane, “A 11.16μJ/token Edge LLM Accelerator with Scalable Ring-based Configuration for Token-wise Pipelining in 16nm FinFET,” IEEE Custom Integrated Circuits Conference (CICC), Seattle, USA, 2026. (Co-Corresponding Author)

[DATE’26] M. Moffatt, J. Luo, H. Cheng, Q. Wang, X. Jiang, G. Tao, S. Liu*, K. Lei, G. Kielian, M. Saligane, “FLARE: Finetuning ReLU With FIRE for Efficient Long-Context Inference,” Design Automation and Test in Europe Conference (DATE), Verona, Italy, 2026. (Co-Corresponding Author)

[DAC’25] S. Liu*, Z. Huang, J. Yu, Q. Liu, C. Chen, “McPAL: Scaling Unstructured Sparse Inference with Multi-Chiplet HBM-PIM Architecture for LLMs,” ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, 2025.

[DAC’25] Z. Huang, S. Liu*, H. Zhu, Q. Liu, C. Chen, “DRAFT: Decoupling Backpropagation from Pre-trained Backbone for Efficient Transformer Fine-Tuning on Edge,” ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, 2025.

[ICCAD’24] S. Liu*, G. Tao, Y. Zou, D. Chow, Z. Fan, K. Lei, B. Pan, D. Sylvester, G. Kielian, M. Saligane, “Consmax: Hardware-friendly alternative softmax with learnable parameters,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), New York, NY, USA, 2024.

[ISSCC’23] S. Liu*, J. Zhang, Y. Wang, H. Zhu, W. Jiang, S. Tang, C. Chen, Q. Liu, M.Liu, “A 28nm 53.8 TOPS/W 8b Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper for Unstructured-Pruned NN and CIM-Based Local-Attention-Reusable Engine,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2023.

[ISCAS’23] J. Liao, B. Jiao, J. Zhang, S. Liu*, H. Jiang, J. Tao, W. Jiang, Q. Liu, L. Zhang, H. Zhu, C. Chen, “A Scalable Die-to-Die Interconnect with Replay and Repair Schemes for 2.5D/3D Integration,” IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, USA, 2023.

[AICAS’22] C. Mu, Y. Wang, J. Zheng, S. Liu*, K. Zhou, S. Tang, C. Chen, Q. Liu, “A 200m-Query-Vector/s Computing-in-RRAM ADC-Less K-Nearest-Neighbor Accelerator with Time-Domain Winner-Takes-All Circuits,” IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), Monterey, CA, USA, 2022.

[GLSVLSI’21] S. Liu*, Z. Zhao, Y. Wang, Q. Zou, Y. Zhang, R. Shi, “Systolic-Array Deep-Learning Acceleration Exploring Pattern-Indexed Coordinate-Assisted Sparsity for Real-Time on-Device Speech Processing,” Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), Virtual Event, USA, 2021.

[AICAS’20] S. Liu*, H. Zhu, C. Chen, L. Zhang, R. Shi, “XNORAM: An Efficient Computing-in-Memory Architecture for Binary Convolutional Neural Networks with Flexible Dataflow Mapping,” IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), Genova, Italy, 2020.

Journal Papers

[TCAS-I’26] H. Jiang, Z. Chen, J. Lu, S. He, L. Lyu, J. Xu, J. Yang, S. Liu*, Y. Chen, C. Chen, Q. Liu, M. Liu, “A 1024-Ch 583-nW/Ch Spike-Sorting SoC With Sparsity-Aware Spike Detection Scratchpad and Ultra-Low-Leakage Dual-Voltage 5T-SRAM for 16K-Template Clustering,” IEEE Transactions on Circuits and Systems I: Regular Papers, 2026. (Co-Corresponding Author)

[JETCAS’26] S. Liu*, J. Yu, P. Li, F. Lin, C. Chen, “Scalable Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper and Local Attention Reusable Engine for Semi-Structured-Pruned NN,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2026.

[TVLSI’23] S. Liu*, C. Mu, H. Jiang, Y. Wang, J. Zhang, F. Lin, K. Zhou, Q. Liu, C. Chen, “Hardsea: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023.

[JETCAS’20] S. Liu, H. Zhu, C. Chen, S. Liu, Q. Zou, M. Wang, L. Zhang, X. Zeng, R. Shi, “A Communication-Aware DNN Accelerator on ImageNet using In-Memory Entry-Counting-Based Algorithm-Circuit-Architecture Co-Design in 65-nm CMOS,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2020.