Research
Chiplet and Multi-Core Architecture
rDXE: Multi-Core TPU Accelerator for LLMs
A 11.16μJ/token Edge LLM Accelerator with Scalable Ring-based Configuration for Token-wise Pipelining in 16nm FinFET [CICC 2026] Edge deploymen...
Read more → In-Memory Computing
1024-Ch 583-nW/Ch Spike-Sorting SoC
A 1024-Ch 583-nW/Ch Spike-Sorting SoC With Sparsity-Aware Spike Detection Scratchpad and Ultra-Low-Leakage Dual-Voltage 5T-SRAM for 16K-Template Clusteri...
Read more → 
ICARUS: Routing-in-Memory Sparse LLM Accelerator
A 28nm 53.8TOPS/W 8b Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper for Unstructured-Pruned NN and CIM-Based Local-Attention-Reusab...
Read more →