High-density Brain-Computer Interfaces require the simultaneous processing of thousands of neural channels, yet they must operate within the extremely tight thermal and power envelopes of implanted electronics. Conventional spike-sorting SoCs face a dual bottleneck:
- Massive leakage power from large on-chip buffers required for multi-channel data
- Dynamic energy waste from continuously monitoring sparse neural signals.
- Supporting a large-scale template library (e.g., 16K templates) for accurate clustering typically leads to prohibitive frequent and energy-intensive off-chip data transfers.
This work presents a 1024-channel spike-sorting SoC that introduces a cross-layer strategy to minimize both static and dynamic dissipation:
- Sparsity-Aware Spike Detection Scratchpad: By implementing a bit-wise differential encoder and zero-friendly readout circuits, the architecture exploits the inherent sparsity of neural firing events to skip redundant computations.
- Ultra-Low-Leakage Dual-Voltage 5T-SRAM: To suppress the “always-on” leakage of neural buffers, the design utilizes a 5T-SRAM array operating at half VDD. This is supported by level-shifter embedded sense amplifiers to maintain signal integrity during readout.
- Hybrid Template Memory Hierarchy: A firing-rate-aware management scheme combines on-chip SRAM with off-chip FeRAM, allowing the system to scale to 16K-template clustering while minimizing high-energy off-chip memory access.
Fabricated in 28nm CMOS, the SoC achieves a state-of-the-art power efficiency of 583 nW/Ch. The system effectively supports real-time sorting for 1024 channels and 16,384 templates, providing a robust and scalable hardware foundation for massive-probing-channel closed-loop BCIs.